1. Field of the Invention
The present invention relates generally to an input circuit for use in a semiconductor integrated circuit (IC) and, more particularly, to an improvement operable at different source voltages. The invention has particular applicability to a MOS IC retaining compatible characteristic with a transistor-transistor logic (TTL) circuit.
2. Description of the Background Art
Recently there have been increasing urgent demands for reducing power consumption in the operations of semiconductor ICs. One of the effective method for meeting such requirements is carried out by lowering a source voltage supplied to the semiconductor IC. In other words, desired reduction of the power consumption can be achieved by applying, instead of 5.0 volts used as a source voltage for the semiconductor IC generally in the present technical stage, a lower source voltage of, e.g. 3.0 volts to the semiconductor IC.
Meanwhile, for constituting requisite circuit configurations adapted for a variety of uses as in a computer system or the like, there are employed circuits formed in a great number of semiconductor chips. The terminals of such semiconductor chips are connected with one another by means of wiring to constitute individual circuits having desired functions. As exemplary ICs formed in such semiconductor chips, there are known a transistor-transistor logic (TTL) circuit and a metal oxide semiconductor (MOS) circuit. Generally a TTL circuit is composed of bipolar transistors, while a MOS circuit is composed of MOS transistors corresponding to one type of field effect transistors.
FIG. 5 is a circuit block diagram of a semiconductor chip (IC device) 100 constituted of an internal processing circuit 101 and MOS circuits 91 through 9n connected respectively to semiconductor chips 81 through 8n including TTL circuits. The semiconductor chip or IC device 100 is connected to receive the outputs of external TTL circuits 81 through 8n. Referring to FIG. 5, the semiconductor chip or IC device 100 comprises input circuits (or input buffer circuits) 91 through 9n connected to receive the respective output signals from the TTL circuits, and an internal processing circuit 101 to perform its function in response to the input signals. The signals thus processed by the circuit 101 are obtained via the output terminals.
FIG. 6 is a connection diagram of the conventional input circuit 91 shown in FIG. 5. Referring to FIG. 6, the input circuit 91 comprises a complementary inverter consisting of a PMOS transistor 23 and an NMOS transistor 24, and diodes 21 and 22 for protecting such inverter against damage by electrostatic charge.
In case the TTL circuit and the MOS circuit are connected to each other, the respective operating currents and voltages are mutually different, so that it becomes necessary to provide a circuit for adjusting the difference therebetween. For this reason, the input circuit 91 shown in FIG. 6 has the so-called TTL compatible characteristic for enabling connection of the TTL circuit 81 to the internal processing MOS circuit 101. Due to such TTL compatible characteristic, a high-level signal "H" is detected with certainty when an input signal of 2.0 volts or more is received; while a low-level signal "L" is detected with certainty when an input signal of 0.8 volt or less is received.
The inverter included in the input circuit 91 shown in FIG. 6 is so designed as to have such TTL compatible characteristic. Generally, the threshold value V.sub.thin of the complementary inverter shown in FIG. 6 is obtained from the following equation in relation to the threshold value V.sub.tp of the transistor 23 and the threshold value V.sub.th of the transistor 24: ##EQU1## where Kp and Kn denotes the current amplification factors of the transistors 23 and 24 respectively.
FIG. 7A graphically shows the TTL compatible characteristic representing an exemplary case of applying a supply voltage of 5.0 volts. As mentioned above, logic "1" is detected in response to any input voltage above 2,0 volts, while logic "0" is detected in response to any input voltage below 0.8 volt.
As shown in FIG. 7A when the threshold value V.sub.thin of the inverter in FIG. 6 is set to 1.4 volt, margins MH1 and ML1 each of about 0.6 volt are obtained with respect to both logic "1" and "0". For enhancing the operational reliability of the logic circuit, it is essential to set mutually equal margins MH1 and ML1 in the inverter of the input circuit 91.
Setting the threshold value V.sub.thin of the inverter to 1.4 volt can be carried out by applying the conditions of Vcc=5.0 volts, V.sub.th =1.0 volt and V.sub.tp =-1.0 volt to Eq. (1) as: ##EQU2##
The amplification factor K of the transistor is calculated from the following equation in relation to its gate length L, gate width W, gate capacitance Cox and carrier mobility .mu.: EQU K=.mu..multidot.Cox.multidot.W/L (3)
Therefore, the value of Kn/Kp to satisfy the condition of Eq. (2) can be obtained by properly setting the respective ratios W/L of the transistors 23 and 23. As a result, there is achieved a complementary inverter having a threshold value V.sub.th of 1.4 volt at the source voltage Vcc of 5.0 volts as shown in FIG. 7A.
The complementary inverter incorporated in the input circuit 91 is designated on the assumption to operate at a predetermined source voltage Vcc (5.0 volts in the above example), hence raising the following disadvantage. That is, when a lower source voltage of 3.0 volts is supplied for the aforementioned purpose of reducing the power consumption, the threshold value V.sub.thin of the inverter becomes about 1.13 volt which is derived from applying the condition of Vcc=3.0 to Eq. (1).
FIG. 7B graphically shows the input characteristic of the complementary inverter indicated when a source voltage Vcc of 3.0 volts is supplied thereto. Since the threshold value of the inverter becomes about 1.13 volt as shown in FIG. 7B, the margin MH2 for logic "1" is increased when the margin ML2 for logic "0" is decreased. Consequently there arises another problem that the internal processing circuit functioning in response to the output signal of the inverter may fail to produce a proper processed result.
The problem caused by the change in the threshold value of the inverter will be understood well when FIG. 8 is referred. FIG. 8 shows the change of the input signal V.sub.in from the "L" level to the "H" level with time. Now, the input signal V.sub.in is assumed to have sharp pulses P1 to P6 having different maximum peak values as noises. The pulses P1 to P3 are superimposed on the input signal V.sub.in of the "L" level, while the pulses P4 to P6 are superimposed on the input signal V.sub.in of the "H" level. As shown in FIG. 8, when the threshold voltage V.sub.thin is 1.4 volt, the output level of the inverter is inverted only by the pulse P3 in the period T1. In the period T2, the output level of the inverter is inverted only by the pulse P6. Meanwhile, if the threshold value V.sub.thin is 1.13 volt, the output level of the inverter is inverted by the pulse P4 as well as the pulse P3 in the period T1. The foregoing shows that the possibility of detecting the "H" level as the input signal V.sub.in is increased by the decrease of the threshold voltage V.sub.thin. In other words, the margin ML2 for the logic "0" is reduced, as described above.